The present invention relates to integrated circuits, and more particularly to nonvolatile memories.
FIGS. 1–4 illustrate a nonvolatile memory fabrication process described in U.S. Pat. No. 6,555,427 issued Apr. 29, 2003 to Shimizu et al. These figures show vertical cross sections of the memory structures. A P-well is formed in a semiconductor substrate 110. Tunnel dielectric 120 is formed on substrate 120 on the P-well. First conductive layer 130.1 is formed on dielectric 120 to provide portions of floating gates for the memory cells. A masking layer 140 is formed on layer 130.1. Layers 140, 130.1, 120 and substrate 110 are etched to form isolation trenches 150. The sidewalls of trenches 150 and the layer 130.1 are oxidized, and dielectric 210 is deposited over the structure. Dielectric 210 is subjected to an etch or chemical mechanical polishing (CMP) to expose the top surface of masking layer 140.
Layer 140 is removed. An isotropic etch of dielectric 210 laterally recesses the dielectric sidewalls away from the floating gate portions 130.1, widening the empty areas above these floating gate portions.
Second conductive layer 130.2 (FIG. 3) is deposited over the structure to provide second portions of the floating gates 130. Layer 130.2 is etched or polished to expose the dielectric 210. A planar top surface is provided. Then dielectric 210 is etched down to expose sidewalls of layer 130.2.
Inter-gate dielectric 410 (FIG. 4) and control gate layer 420 are formed over the structure to finish the memory cell fabrication.
The memory cells are programmed by injecting a negative charge (electrons) into their floating gates 130. The cells are erased by removing the negative charge from the floating gates. The cells are read by sensing the charge on the floating gates. These operations require a voltage VFG.S to be induced between the floating gate (FG) 130 and a region of substrate 110. The voltage VFG.S is induced by establishing a voltage VCG.S between the control gate (CG) 420 and the substrate region, as the control gate is capacitively coupled to the floating gate. In order to reduce the maximum voltage VCG.S needed to induce a given voltage VFG.S, one has to increase the “gate coupling ratio” CCG.FG/CFG.S, where CCG.FG is the capacitance between control gate 420 and floating gate 130, and CFG.S is the capacitance between the floating gate 130 and the substrate region. The isotropic etch of dielectric 210 (FIG. 2) serves to increase CCG.FG due to the increased width of the top floating gate portions 130.2 (FIG. 3). The etch-back of dielectric 210 (FIG. 3) to expose the sidewalls of layer 130.2 further increases the capacitance CCG.FG by increasing the capacitive coupling between the sidewalls of layer 130.2 and the control gate 420.